1. Field of the Invention
This invention relates to power inverter and converter circuits and to improving the switching efficiency of its power switching transistors. In particular, it relates to turn-off loss reduction networks to improve the switching efficiency of power switching transistors during a switching transition from conduction to nonconduction intervals.
2. Description of the Prior Art
Power inverter and converter circuits utilize power switching transistors, coupled to a voltage transformer, in order to invert a DC voltage to derive an AC voltage. For AC-to-DC converters, this AC voltage is rectified to produce DC again. During the turn-off transition of the switching transistor, as the collector current decreases from a high value to zero, collector-to-emitter voltage rises abruptly due to the energy stored in the leakage inductance in the primary circuit of the inverter, and a significant amount of power is dissipated within the power switching transistor. The occurrence of high collector-emitter voltage during the turn-off interval could give rise to a secondary breakdown in the transistor, which is analogous to an arcing condition within the transistor and precipitate its failure. This power dissipated in the transistor not only reduces overall inverter efficiency, but requires large heat exchange devices to remove the heat from the transistor in order to maintain the transistor temperature within safe limits.
Because of this danger of secondary breakdown to the power switching transistor in high power inverter circuits, and to reduce the power dissipated in the transistors, turn-off loss reduction networks are used to control the rate of voltage rise across the power switching transistor during the turn-off transition period. Most turn-off loss reduction networks utilize the principle that the voltage across a capacitor is proportional to the time integral of the current through the capacitor in order to limit the rate of rise of the collector-emitter voltage as the power switching transistor turns off.
A typical turn-off loss reduction network comprises a series-connected diode and a capacitor connected in parallel with the main conduction path of the power switching transistor. The capacitor in the turn-off loss reduction limits the rate of rise in the collector-emitter voltage during the transition from conduction to nonconduction, as it charges from near zero to the off-state collector-emitter voltage. During the next subsequent conduction interval of the power switching transistor, however, the capacitor is discharged to the low saturated collector-emitter voltage of the conducting power transistor.
Typical capacitor discharge circuits for a turn-off loss reduction network use a resistive discharge path. This circuit has the advantage of simplicity; however, the energy saved by the turn-off loss reduction network during the turn-off switching transition is lost in the resistive discharge path during the following conduction interval of the power transistor. This power loss can be significant in the case of high power inverter circuits and is dissipated as heat within the inverter equipment.
The power dissipation of the discharge path is intensified in push-pull or double-ended type inverter designs, since due to the auto transformer effect of the center tapped primary winding of an inverter power transformer, the capacitive charge and discharge cycle associated with the turn-off loss reduction network of each power switching transistor occurs twice during each cycle of operation of the inverter circuit.
It is important then that turn-off loss reduction circuitry utilized to improve efficiency of the switching of the power switching transistor of a high power inverter be operated to eliminate the aforedescribed double charge/discharge occurrence and further include a low loss discharge path to reduce power dissipation as much as possible during the discharge cycles of the capacitors included in the turn-off loss reduction network.
Two examples of turn-off loss reduction networks, using high efficiency discharge paths to reduce loss during the discharge of the capacitor, are disclosed in U.S. Pat. No. 4,015,185 issued to Werner Pollmeier on Mar. 29, 1977 and in an article entitled "Designing Non-Dissipative Current Snubbers For Switched Mode Converters" by Eugene C. Whitcomb published in the Proceedings of POWERCON 6 May 1979. The turn-off loss reduction networks disclosed therein utilize a nondissipative turn-off loss reduction network using resonant LC charging and discharging paths to control the network's capacitor charge. Steering diodes are utilized to couple the capacitor to supply current, at the turn-off of the switching transistor, to an output filter in order to replace current previously supplied thereto by the now turned-off switching transistor. These circuits, however, are limited by being completed dependent on resonant circuit action and are susceptible to premature partial discharge whenever the voltage across the transistor drops below the peak value attained. These circuits are both disclosed with reference to single-ended type inverter circuits. They are not effective in the double-ended inverter circuits, since the premature discharge phenomenon referred to above interferes with the desired operation.